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IASI Research Report n. 291 (Next) Antenucci G.,
Sara Nicoloso,
Simeone B.Optimal hypergraph partitioning in VLSI circuit layout.ABSTRACT A crucial stage in VLSI circuit design is partitioning the components into "pages" with given capacity. it is usually desirable that each net crosses as few pages as possible. This leads to an NP-complete weighted hypergraph partitioning problem. Since hypergraphs arising from real-life VLSI applications are extremely large, it is out of question to use exact solution methods, as well as heuristics whose complexity is not linear in the number of nodes or edges of the hypergraph. In the present paper we describe three heuristics which achieve a resonable trade-off between low complexity and closeness to optimality and we discuss the results of an experimental comparison of the three heuristics on large test problems, which have been randomly generated so as to simulate the structure of real-life problems.